[kwlug-disc] Refurb laptops & monitors - Eco-Tech Recycling?

[John Johnson]

respectfully.

Following the Wikipedia link (provided) on Dual Channel Architecture I 
found the Intel link to "Single, dual, triple and flex memory modes" 
<http://www.intel.com/support/motherboards/desktop/sb/cs-011965.htm>, at 
the bottom of the wiki page.
Following the Intel link to "Single, dual, triple and flex memory modes" 
<http://www.intel.com/support/motherboards/desktop/sb/cs-011965.htm>, I 
found the following text:

*Dual-channel (interleaved) mode*
This mode offers higher memory throughput and is enabled when the memory 
capacities of both DIMM channels are equal. When using different speed 
DIMMs, the slowest memory timing is used.

Dual Channel Architecture is not the same as Interleaving which I 
attempted to explain earlier.

This Wikipedia link describes interleaving: 
http://en.wikipedia.org/wiki/Interleaved_memory

I know these links describe Dynamic Random Access Memory (DRAM) which is 
a term that goes back to the 1980s. More on this below.

IMHO, in neither the Intel link nor the Wikipedia link (above), is the 
"why" explained - even briefly.

The Wikipedia article does include the text: "That way, contiguous 
memory reads and writes are using each memory bank in turn, .... "
I think this text would be more correctly written: "That way, 
*/successive/* memory reads and writes are using each memory bank in 
turn, .... "

Here, I will attempt to briefly explain the "why" as far as I can do so, 
because it has been a long, long time since I have studied the 
semiconductor physics involved.

With certain types of semiconductor memory, any read or write action, 
will change the internal state of the memory cell for a brief time. With 
writes, the length time the state of memory cell is changed is longer 
than with a read. The result of another read or write action during the 
time the internal state of the memory cell is "in flux" would be unreliable.

I would expect that the underlying semiconductor physics involved with 
DRAM carries through to the technologies which followed, e.g. DDRx, 
multi-channel, etc.

Further, I would expect, that the interleaving is still buried "deep 
down inside" (*) within the DDRx and other memory management technologies.

* I tossed in a Pink Floyd reference going back to a time when I knew 
more about semiconductor physics than I do now.

PS: The timing of successive reads is also an issue with EPROM. And for 
the same reason, i.e. the semiconductor physics involved. In a PBX 
product I worked with in the 1980s and 1990s, the designers employed 
interleaving to distribute the executable code, in 16 bit words, among 
two banks of pairs of 8 bit EPROM ICs. Successive 16 bit words, were in 
separate pairs of EPROM ICs. The executable code generated by the 
compiler was processed by a "splitter" application to generate the 
bank0-high-byte, bank0-low-byte, bank1-high-byte, bank1-low-byte, etc. 
image required for burning the EPROMs.

John Johnson

On 2014-04-24 23:08, unsolicited wrote:
> https://en.wikipedia.org/wiki/Dual-channel_architecture#Dual-channel_architecture 
>
>
> On 14-04-24 06:11 PM, John Johnson wrote:
>> On 2014-04-24 10:37, unsolicited wrote:
>>> It's long been known to install memory in pairs.
>>
>> "It is known" is not the same as "knowing why".
>>
>> I was trying to explain the "why" memory is installed in pairs, at least
>> on older machines.
>> I am not sure, but I think the "pairing" is now done in the modules
>> themselves (or, at least, in some types of memory modules).

< ... snip ... >

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