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respectfully.<br>
<br>
Following the Wikipedia link (provided) on Dual Channel Architecture I
found the Intel link to <span id="CITEREF" class="citation"><a
rel="nofollow" class="external text"
href="http://www.intel.com/support/motherboards/desktop/sb/cs-011965.htm">"Single,
dual, triple and flex memory modes"</a>, </span>at the bottom of the
wiki page.<br>
Following the Intel link to <span id="CITEREF" class="citation"><a
rel="nofollow" class="external text"
href="http://www.intel.com/support/motherboards/desktop/sb/cs-011965.htm">"Single,
dual, triple and flex memory modes"</a>, </span>I found the following
text:<br>
<br>
<strong>Dual-channel (interleaved) mode</strong><br>
This mode offers higher memory throughput and is enabled when the
memory capacities of both DIMM channels are equal. When using different
speed DIMMs, the slowest memory timing is used.<br>
<br>
Dual Channel Architecture is not the same as Interleaving which I
attempted to explain earlier.<br>
<br>
This Wikipedia link describes interleaving: <a
href="http://en.wikipedia.org/wiki/Interleaved_memory">http://en.wikipedia.org/wiki/Interleaved_memory</a><br>
<br>
I know these links describe Dynamic Random Access Memory (DRAM) which
is a term that goes back to the 1980s. More on this below.<br>
<br>
IMHO, in neither the Intel link nor the Wikipedia link (above), is the
"why" explained - even briefly.<br>
<br>
The Wikipedia article does include the text: "That way, contiguous
memory reads and writes are using each memory bank in turn, .... "<br>
I think this text would be more correctly written: "That way, <big><b><i>successive</i></b></big>
memory reads and writes are using each memory bank in turn, .... "<br>
<br>
Here, I will attempt to briefly explain the "why" as far as I can do
so, because it has been a long, long time since I have studied the
semiconductor physics involved.<br>
<br>
With certain types of semiconductor memory, any read or write action,
will change the internal state of the memory cell for a brief time.
With writes, the length time the state of memory cell is changed is
longer than with a read. The result of another read or write action
during the time the internal state of the memory cell is "in flux"
would be unreliable.<br>
<br>
I would expect that the underlying semiconductor physics involved with
DRAM carries through to the technologies which followed, e.g. DDRx,
multi-channel, etc. <br>
<br>
Further, I would expect, that the interleaving is still buried "deep
down inside" (*) within the DDRx and other memory management
technologies.<br>
<br>
* I tossed in a Pink Floyd reference going back to a time when I knew
more about semiconductor physics than I do now.<br>
<br>
PS: The timing of successive reads is also an issue with EPROM. And for
the same reason, i.e. the semiconductor physics involved. In a PBX
product I worked with in the 1980s and 1990s, the designers employed
interleaving to distribute the executable code, in 16 bit words, among
two banks of pairs of 8 bit EPROM ICs. Successive 16 bit words, were in
separate pairs of EPROM ICs. The executable code generated by the
compiler was processed by a "splitter" application to generate the
bank0-high-byte, bank0-low-byte, bank1-high-byte, bank1-low-byte, etc.
image required for burning the EPROMs.<br>
<br>
John Johnson <br>
<br>
On 2014-04-24 23:08, unsolicited wrote:
<blockquote cite="mid:5359D1AF.3090704@swiz.ca" type="cite"><a class="moz-txt-link-freetext" href="https://en.wikipedia.org/wiki/Dual-channel_architecture#Dual-channel_architecture">https://en.wikipedia.org/wiki/Dual-channel_architecture#Dual-channel_architecture</a>
<br>
<br>
On 14-04-24 06:11 PM, John Johnson wrote:
<br>
<blockquote type="cite">On 2014-04-24 10:37, unsolicited wrote:
<br>
<blockquote type="cite">It's long been known to install memory in
pairs.
<br>
</blockquote>
<br>
"It is known" is not the same as "knowing why".
<br>
<br>
I was trying to explain the "why" memory is installed in pairs, at
least
<br>
on older machines.
<br>
I am not sure, but I think the "pairing" is now done in the modules
<br>
themselves (or, at least, in some types of memory modules).
<br>
</blockquote>
</blockquote>
<br>
<tt>< ... snip ... ></tt><br>
<br>
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